MTJs (Magnetic Tunnel Junction) and GMR (giant magneto-resistance) devices of MRAM cells are programmed by the cross point effect of word line and bit line currents. A major concern is the problem of cells on the same word line and bit lines being disturbed. Segmented word line approaches, as described for example in “Select Line Architecture for Magnetic Random Access Memories” (US patent application Publication: U.S. 2002/0176272 A1), eliminate the disturb condition for cells that are on the same word line but in a different segment.
A typical segmented word line array of the prior art is shown FIG. 1. The word line programming current goes through only the selected segmented word line source, the selected word line segment, and the word line segment select transistor to the segmented word line return. Thus, any memory elements outside this word line segment are not affected by the programming current.
Seen in FIG. 1 are read word line 11, write word line 12, and bit lines 13. Each of the latter intersects segmented word line 14 (which is driven by segment selection transistor 15) at a memory storage element 16 where a local magnetic field is generated that is strong enough to influence the device's free layer. The state of the free layer is detected during the read cycle when isolation transistor 17 is activated by read world line 11. It is important to note that segment selection transistor 15 is located so that it connects the segment 18 directly to the current source return line.
So, in this design, the word line current source of word line segments are all connected together. As the array grows, the capacitance associated with these word line segments becomes large enough to cause a number of problems. Loading and noise due to coupling between the word lines and bit lines are obvious examples. The charge stored on a word line segment can produce a big enough current spike to disturb bytes controlled by the same write word line when a byte on other blocks is being programmed. The present invention discloses a method of eliminating these problems.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,335,890 (Roehr et al) discloses global and local word lines where the global word lines are isolated from the memory cells, write lines and bit lines orthogonal, and a switch for each word line segment. The gate terminal is “operatively connected to the group select signal, and the drain and source terminals being operatively connected between the write line current return conductor and the segmented write line conductor corresponding to the segmented group.”
U.S. Pat. No. 6,490,217 and U.S. Patent Application 200210176272 (DeBrosse et al) teach the word line current source of all the word lines connected together.
U.S. Pat. No. 5,315,541 (Harari et al) shows two select transistors, one on the drain bit line and on the source bit line.
U.S. Patent Application 2004/0047172 (Komatsuzaki) teaches segmented word lines, bit lines, and plate lines.